1553 Intellectual Property (IP) Core

Intellectual Property (IP) Core is a logic or data block used to build a Field Programmable Gate Array (FPGA) or Application-Specific Integrated Circuit (ASIC) for a product. In terms of design reuse, IP Cores are an important part of the electronics design industry as they allow pre-designed components to be used repeatedly. MIL-STD-1553 standard defines three terminal units. These are a bus controller, remote terminal, and bus monitor. The functions of these three terminals have been made software-based using HDL. The designed 1553 IP Core can be programmed as a Bus controller, Remote terminal, or Bus monitor depending on the user's choice. IP Core is designed to meet the requirements of the MIL-STD-1553B Notice2 standard.

Key Features

  • Operates with a 16 MHz clock pulse
  • Utilizes a 16-bit bus
  • Capable of error detection and reporting
  • Complies with MIL-STD-1553B standard
  • Allows broadcast and redundant communication
  • Detects illegal commands
  • Monitors traffic on the bus
  • Facilitates data exchange between the bus and host